Clock synchronization devices attempt to synchronize communication between two devices in different or independent clock domains or time domains. For example, the communication between a processor in a fast clock domain and a memory device in a slow clock domain may require synchronization in order for the devices to communicate (e.g., for the processor to access data stored in the memory device). Memory access synchronization may require that the memory be aware of which address or resource is being accessed by a processor.
FIGS. 1A and 1B show conventional designs for synchronizing access information. Specifically, FIG. 1A shows a conventional system 100 with an arrangement of flip-flops 104 and 106 for synchronizing information between time domains with a core or slow clock 108. The asynchronous read/write enable signal 102 is synchronized via the core clock 108 or slower clock. This design requires that the pulse width of the clock signal has to be larger than the clock period or the clock signal that samples it. For example, if the core is running at 100 Mhz, the clock period will be 10 ns and the read/write strobe is required to be greater than 10 ns. Otherwise, if the width of the read/write strobe was less than 10 ns (e.g., 5 ns) the read/write strobe can change during the clock period and the core clock will not see the change. Thus, a restriction is placed on the pulse width so that it is larger than the clock period of the clock being used to sample.
FIG. 1B shows another conventional system 110 with an arrangement of flip-flops 114, 116 and 117 for synchronizing information between time domains via a fast clock 118 and core clock 120. The fast clock is used to remove the restriction placed on the pulse width of the previous conventional design by using the fast clock to sample frequently enough that a greater range of pulse widths are supported. For example, if the core is operating at 100 Mhz and the fast clock runs at 1 Ghz, the samples will be every 1 ns and thus the pulse width can be one to two ns. Unfortunately, a high speed clock increases the physical complexity of this circuit and requires more power and is more complex to design, expensive, etc.
Thus, conventional synchronization designs have unfortunate pulse width restrictions or increased complexity and power requirements.